|
Conversion method
|
Wilkinson’ s
|
|
Conversion clock frequency
|
100 MHz
|
|
Analogue input signal
|
Polarity
|
Positive |
|
Amplitude
|
50 mV - 10 V
|
|
Rise time
|
> 0.25 µs
|
|
Decay time
|
< 100 µs
|
|
Input resistance |
2 k Ω |
|
Differencial nonlinearity (DNL)
|
< 1 %
|
|
Integral nonlinearity (INL)
|
< 0.04 % |
|
Software-adjusted channel width with adjustment step
|
5 µV
|
|
Channel width setting accuracy |
5 % |
| Temperature instability of the channel width |
< 0.01 % |
|
Channel memory capacity
|
224 - 1
|
|
Real/live time setting accuracy
|
5 ms
|
|
Lower-level discriminator threshold range
|
30 mV - 10 V
|
|
Upper-level discriminator threshold range
|
100 mV - 10 V
|
|
“Ratemeter” input - logical signal with frequency up to 300 kHz
|
+ |
|
“Inhibit” input with programmable polarity
|
+
|
|
Overall dimensions
|
215x105x33 mm
|
